This invention relates to the field of integrated circuit fabrication. More particularly, the invention relates to forming metal-insulator-metal capacitor structures, pad structures, and fuse structures.
Metal-insulator-metal capacitors are widely used in mixed signal CMOS integrated structures because of the ability to precisely control their capacitance based on dimensional control. Metal fuses are also widely used to provide redundancy in embedded CMOS memory, thereby increasing the yield of application-specific integrated circuits. Processes for forming a metal-insulator-metal capacitor structures and fuse structures in integrated circuits have generally required several photomask, pattern, and etch steps to form the capacitors, and several more such process steps to form the fuses. Each photomask, pattern, and etch step adds significant cost, process time, and potential for error to the overall circuit fabrication process.
What is needed, therefore, is a process for forming metal-insulator-metal capacitor and fuse structures using fewer photomask, pattern, and etch steps.
The above and other needs are met by a process for simultaneously forming a capacitive structure and a fuse structure in an integrated circuit device. The process includes forming a first capacitor plate and first and second fuse electrodes in a first dielectric layer of the device. In a second dielectric layer overlying the first dielectric layer, a capacitor dielectric section overlying the first capacitor plate, and a fuse barrier section overlying and between the first and second fuse electrodes are formed simultaneously. In a conductive layer overlying the second dielectric layer, a second capacitor plate overlying the capacitor dielectric section, and a fuse overlying the fuse barrier section and contacting the first and second fuse electrodes are formed simultaneously.
In various preferred embodiments of the invention, the capacitor dielectric section and the fuse barrier section are defined simultaneously by selectively removing portions of the first dielectric layer, such as during a single etching step. Also in preferred embodiments of the invention, the second capacitor plate and the fuse are defined simultaneously by selectively removing portions of the conductive layer, such as during a single etching step. Thus, the invention provides for forming various structures of the capacitor and the fuse during the same photomask, patterning, and etching steps, thereby reducing fabrication cost and time.
In another preferred embodiment, the process includes forming a dielectric layer over the capacitor and the fuse, and subsequently selectively removing a portion of the dielectric layer over the fuse such that a desired thickness of the dielectric layer remains over the fuse. The desired thickness of the dielectric layer over the fuse introduces a minimal amount of absorption to laser energy that is subsequently used to blow the fuse during programming of memory on the integrated circuit device. In this manner, a minimal level of laser energy is needed to blow the fuse, thereby reducing the risk of dielectric cracking caused by the absorption of excess laser energy, and reducing laser exposure of the first dielectric layer underlying the fuse structure.